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    • 专利摘要:
    In the photolithographic step of providing the resist film 12 having the window 12a formed on the surface of the silicon wafer 10 at the time of manufacturing the dielectric separation wafer, the backside resist 12A is applied to the silicon wafer 10 , And the entire backside resist 12A is bridged by the entire exposure. Thereby, at the time of developing / rinsing avoiding the filling of the window portion 12a by the resist 12A when the backside resist 12A is completely diffused toward the wafer surface side after the application of the backside resist 12A, It is possible to prevent the spoilage. Further, the surface of the dielectric separation wafer on which the dielectric isolation silicon island 10A is formed is polished, and then low-temperature polysilicon is deposited on the surface of the dielectric separation wafer by CVD, or SOG is applied and fired. As a result, the concave portion 16a generated at the time of polishing the surface of the dielectric separation wafer is buried by the low-temperature polysilicon layer 30 or the SOG layer. Subsequently, the low-temperature polysilicon layer 30 or the SOG layer is polished away from the surface. At this time, the portion where the concave portion 16a of the wafer surface is buried remains. As a result, the surface of the dielectric separation wafer can be planarized.
    公开号:KR20010025124A
    申请号:KR1020007014735
    申请日:1999-06-22
    公开日:2001-03-26
    发明作者:히로유끼 오이
    申请人:가와이 겐이찌；미쯔비시 마테리알 실리콘 가부시끼가이샤；
    IPC主号:
    专利说明:

    [0001] DIELECTRIC SEPARATION WAFER AND PRODUCTION METHOD THEREOF [0002]
    A general dielectric separation wafer is formed by forming a groove for dielectric isolation on the surface of a silicon wafer, then laminating a dielectric isolation oxide film thereon, and thereafter forming a dielectric isolation oxide film on the silicon wafer by a high temperature CVD (Chemical Vapor Deposition) By growing the polysilicon layer to a thickness of approximately the wafer thickness and then continuously grinding and polishing the silicon single crystal from the silicon wafer side.
    However, in the dielectric separated wafers produced by this method, only wafers up to 4 inches in diameter could be produced depending on the total thickness and degree of warpage. Thus, recently, a bonded dielectric separated wafer in which a wafer for an active layer, which is a dielectric separation wafer, and a wafer for a supporting substrate for supporting the wafer are bonded to solve the problem of large-scale wafer curing has been developed.
    The bonded dielectric separated wafer is manufactured through the respective steps in the explanatory drawing showing the manufacturing process of the general bonded dielectric separated wafer of FIG. Hereinafter, a bonded dielectric separated wafer will be described with reference to FIG.
    First, a silicon wafer 10 whose surface has been subjected to a mirror-finished surface to be a wafer for an active layer is prepared (see Fig. 5 (a)). Subsequently, a mask oxide film 11 is formed on the top and bottom surfaces of the silicon wafer 10 (see FIG. 5 (b)), and a negative resist film 12 having the window 12a formed by photolithography is formed do. Through this window, a window of a predetermined pattern is formed in the oxide film 11, and the surface of the silicon wafer 10 is exposed. Next, this silicon wafer 10 is immersed in an etching solution (isopropyl alcohol (IPA) / KOH / H 2 O) to anisotropically etch the inside of the window portion 12a of the wafer surface (see FIG. Thus, a V-shaped dielectric isolation groove 13 is formed on the surface of the wafer. Here, the anisotropic etching here refers to etching which is caused by the crystal plane orientation of the silicon wafer 10, in which the etching rate in the depth direction is larger than the horizontal direction and the etching rate has direction dependency.
    Next, the negative resist film 12 is removed, and the exposed mask oxide film 11 is cleaned and removed with a diluted HF solution (see Fig. 5 (d)). Thereafter, a dopant (Sb, As, etc.) may be thermally diffused or ion-implanted into the silicon wafer 10, if necessary. Then, a dielectric isolation oxide film 14 is formed on the wafer surface by an oxidative heat treatment (see FIG. 5 (e)). As a result, the dielectric isolation oxide film 14 is also formed on the dielectric isolation trench 13. Next, the wafer surface is cleaned.
    Subsequently, a seed amorphous silicon layer or a seed polysilicon layer 15 is deposited on the surface of the silicon wafer 10 by low-temperature CVD at about 600 ° C (about 550 to 700 ° C). After cleaning, the high-temperature polysilicon layer 16 is grown thickly on the seed amorphous silicon layer or the seed polysilicon layer 15 by high-temperature CVD at about 1250 ° C (about 1200 to 1300 ° C) ) Reference). Then, the outer peripheral portion of the wafer is chamfered, and the back surface of the wafer is planarized as necessary. Then, the high-temperature polysilicon layer 16 on the wafer surface is ground and polished to a thickness of 10 to 80 m, preferably 20 to 50 m (see Fig. 5 (g)). Thereafter, a low-temperature amorphous silicon layer or polysilicon layer 17 having a thickness of 1 to 5 mu m, preferably about 2 to 3 mu m, is formed on the wafer surface by low-temperature CVD at about 600 DEG C (550 to 700 DEG C) The surface of the low-temperature amorphous silicon layer or the polysilicon layer 17 is polished for the purpose of mirror-surfacing (joining) the bonding surfaces.
    On the other hand, a silicon wafer 20 (covered with a silicon oxide film 21 here) serving as a wafer for a support substrate is prepared (see FIG. 5 (h)). This is a mirror surface machining of the wafer surface. Next, the silicon wafer 10 for the active layer wafer is brought into contact with the mirror faces on the silicon wafer 20 (see FIG. 5 (i)). Then, a heat treatment is performed to increase the bonding strength of the bonded wafer. 5 (j), the outer peripheral portion of the active layer silicon wafer 10 is chamfered, and if necessary, the oxide film 21 of the silicon wafer 20 for the support substrate is subjected to HF cleaning And the silicon wafer 10 for the active layer is ground and polished.
    The amount of grinding of the silicon wafer 10 for the active layer is set such that the dielectric separating oxide film 14 is exposed to the outside and the dielectric separating oxide film 14 partitioned by the dielectric separating oxide film 14 on the surface of the high- (10A) is exposed and the adjacent silicon islands are completely separated from each other. Thus, a bonded dielectric separated wafer is produced.
    As described above, the photolithographic method is employed to form the window 12a for anisotropically etching the dielectric isolation trench 13 in the negative resist film 12 of the silicon wafer 10. [
    The photolithographic method is a method of writing a pattern on the surface of a negative resist film 12 coated on a silicon wafer 10 by exposure and then developing it. Hereinafter, the flow of the photolithographic process will be described with reference to the explanatory diagram of the general photolithographic process of FIG.
    The negative resist 12 is first applied to the surface of the silicon wafer 10 (see FIG. 6A) on which the mask oxide film 11 is formed and the solvent in the negative resist film 12 after coating is effectively Remove. Subsequently, the negative resist film 12 is exposed and developed and rinsed (see Fig. 6 (b)). As a result, a window 12a for anisotropic etching is formed in the negative resist film 12 on the wafer surface. Thereafter, the silicon wafer 10 may be charged into a baking furnace to accelerate the cross-linking reaction of the surface negative resist film 12, thereby performing stronger post-baking. Then, in order to prevent the back side of the mask oxide film 11 covering the silicon wafer 10 from being melted by the etching solution during the anisotropic etching of the subsequent process, the negative resist 12A is applied to the back surface of the wafer. Specifically, the negative resist film 12A is applied to the back surface of the wafer by reversing the silicon wafer 10 (see FIG. 6C), put in the baking furnace, and the front side negative resist films 12 and 12A Post-baking to promote the crosslinking reaction of the negative resist films 12 and 12A (see Fig. 6 (d)).
    In this general method, when the negative resist 12A is applied to the back surface of the silicon wafer 10, the backside negative resist 12A is diffused all over the surface side of the wafer periphery, (See Figs. 6 (c) and 6 (d)) of the window 12a for the dielectric separating groove 13 formed in the window 12. Therefore, a conventional means for solving this problem has been developed.
    That is, after the negative resist 12A is applied to the back surface of the silicon wafer 10, as shown in FIG. 7 (c1) of the photolithographic process according to the conventional means of FIG. 7, 10, and then developing and rinsing is performed from the wafer surface side to clean and remove a part of the backside negative resist 12A adhered in the window portion 12a. 7 (a) to 7 (d) in FIG. 7 carry out the same working steps as the corresponding steps in FIGS. 6 (a) to 6 (d).
    However, according to such a conventional method for manufacturing a dielectric separation wafer, in order to solve the problem of filling the window portion 12a by the part of the backside negative resist 12A that has turned to the wafer surface side, The second developer is transferred to the back side of the silicon wafer 10 as opposed to going to the surface side of the backside negative resist 12A shown in Fig. 7C when developing / rinsing the second wafer surface I will return. As a result, the periphery of the negative-side reverse-side negative resist 12A is melted by the second developer, and sawtooth-like irregularities are formed in the peripheral portion of the silicon wafer 10 through the melted portion at the time of anisotropic etching . These irregularities cause cracks in the wafer during handling of the wafer or cause cracking or breakage in the high-temperature polysilicon forming process of the subsequent process.
    According to such a conventional method for manufacturing a dielectric separation wafer, the surface of the active layer wafer 10 is ground in the finishing step of the bonded dielectric separation wafer, and the ground surface is subjected to polishing using the alkaline- (Si island: 10A) partitioned by the silicon oxide layer 14 is exposed.
    8, a concave portion 16a is formed on the polished surface of the active layer wafer 10 in accordance with the difference in polishing rates of the respective layers 10A, 14, and 16 constituting the surface It happens. Particularly, in the grain boundary portion in which the high-temperature polysilicon layer 16 grown according to the V-groove type dielectric isolation oxide film 14 is integrated, etching is performed in comparison with the portions of the other dielectric-isolated silicon island 10A and the dielectric- The recessed portion 16a having a depth of about 0.3 mu m may be formed.
    If such a deep step is formed, for example, in the photolithographic process when a device is manufactured on the user side after shipment of the product, the resist on the wafer surface may interfere with uniform application, circuit breakage or deterioration of resolution may occur There is a possibility that a part of the film may remain on the surface of the wafer at the time of removing the resist film after exposure. Also, in the other steps, the concave portion 16a serves as a dust adsorption site. Moreover, dust adhering to the concave portion 16a usually has a problem that it can not be easily removed because the width of the concave portion 16a is narrow.
    DISCLOSURE OF THE INVENTION <
    Even if the developer at the time of development of the surface negative resist after application of the back side negative resist is diffused all over the back side of the wafer, if the back side negative resist is coated on the silicon wafer and then the whole back side negative resist film is subjected to cross- It was found that the vicinity of the outer periphery of the negative resist film was not fused, thereby completing the first invention of the present invention.
    The first invention is a dielectric separating wafer which can prevent the vicinity of the periphery of the negative resist film coated on the back surface side of the wafer from being damaged by the developer during the development of the surface negative resist after application of the back side negative resist in the photolithographic process, And a method for producing the same.
    A first aspect of the present invention is to prevent breakage of a part of the back side negative resist film in the method of manufacturing a bonded dielectric separated wafer.
    In the first invention, a front surface of a silicon wafer is covered with a mask oxide film, a resist film having a window formed on the surface of the mask oxide film is formed, and a window of a predetermined pattern is formed in the mask oxide film using the resist film as a mask, A part of the surface of the silicon wafer is exposed, anisotropically etching a part of the surface of the exposed silicon wafer to form a dielectric isolation groove, a dielectric isolation oxide film is formed on the surface of the silicon wafer, a polysilicon layer is grown on the dielectric isolation oxide film, And a silicon island separated from the dielectric isolation oxide film is exposed on the polished surface of the silicon wafer, wherein the step of providing a resist film on which the window is formed comprises the steps of: Step of applying resist A step of forming a window of a predetermined pattern on the negative resist film, a step of applying a negative resist to the mask oxide film on the back side, a step of performing front exposure on the backside negative resist film, And removing the adhered back side negative resist.
    As a method for growing the polysilicon layer, a high-temperature CVD method can be employed. This is a method of introducing a raw material gas containing silicon into a reaction furnace together with a carrier gas (H 2 gas or the like) and precipitating silicon produced by thermal decomposition or reduction of the raw material gas on a silicon wafer heated to a high temperature. As the compound containing silicon, SiCl 4 , SiHCl 3 and the like are generally used.
    As the reaction furnace, there is a vertical furnace (pancake furnace furnace) in which a susceptor loaded with a silicon wafer is heated while being heated by high frequency induction in a dome-shaped quartz bell jar. In addition, a silicon wafer is attached to each surface of a hexagonal column-shaped susceptor housed in a quartz container, and thereafter the susceptor is heated in a gas furnace and heated by an infrared lamp in a cylindrical furnace ) Can also be employed.
    The growth temperature of the polysilicon depends on the heating method of the furnace. The most common type used for this purpose is 1,200 to 1,290 캜, particularly 1,230 to 1,280 캜. When the temperature is less than 1200 ° C, there arises a problem that the silicon wafer tends to be cracked. If the temperature exceeds 1290 占 폚, slip occurs, and the silicon wafer tends to be cracked.
    The thickness of the polysilicon layer is a thickness obtained by adding the thickness of the polysilicon layer to be left to the thickness of 2 to 3 times the depth of the anisotropic etching. When the thickness of the polysilicon layer is not more than twice the depth of the anisotropic etching, the grooves of the anisotropic etching may not be sufficiently filled. On the other hand, it is unnecessarily thickly deposited at three times or more, which is uneconomical.
    Further, in the case of forming the diffusion layer on the wafer for the active layer, if the thermal history is unnecessarily elongated, the diffusion profile changes greatly, which is inappropriate.
    As the anisotropic etching solution, an alkaline etching solution such as KOH (IPA / KOH / H 2 O), KOH (KOH / H 2 O), KOH (hydrazine / KOH / H 2 O) As an anisotropic etching condition, ordinary conditions can be applied.
    In addition, general conditions can be employed as the conditions of each process for forming a window for anisotropic etching in the negative resist film on the wafer front surface side.
    In addition, ordinary exposure conditions can be employed as the conditions for the entire exposure of the backside negative resist film, which is a feature of the present invention.
    In the method of manufacturing a dielectric separation wafer according to the first invention of the present application, the dielectric separation wafer may be a bonded dielectric separation wafer produced by bonding a wafer for an active layer in which the dielectric isolation islands are formed and a wafer for the support substrate.
    According to the first invention, a mask oxide film is formed on the top and bottom surfaces of a silicon wafer.
    Subsequently, a negative resist film having a window formed on the surface of the silicon wafer is formed. That is, a negative resist is applied to the surface of a silicon wafer, and a predetermined pattern is exposed on the mask oxide film using the negative resist film as a mask. Further, after the exposure, development and rinsing treatment may be carried out to carry out post-baking.
    Thereafter, the silicon wafer is inverted, and a negative resist is coated on the wafer backside of the mask oxide film. This is spin application.
    Subsequently, the negative resist film on the back side is exposed to the whole surface, thereby allowing the entire backside negative resist film to proceed the crosslinking reaction. As a result, the backside negative resist film is given chemical resistance to the developer.
    Next, the silicon wafer is directly turned to perform development processing of the surface negative resist film after exposure. This phenomenon is a second development processing that avoids filling of the window formed by the negative resist, which is entirely diffused toward the wafer surface side, when the surface negative resist film is developed immediately after exposure of the surface negative resist film.
    At this time, even if the developer flows to the back side of the silicon wafer and adheres to the peripheral portion of the backside negative resist film, there is little possibility that the portion is molten. This is because the chemical resistance of the negative resist film is increased by the front exposure.
    Thereafter, the silicon wafer covered with the front and back negative resist films is immersed in an etching solution to anisotropically etch the mask oxide film and a part of the silicon wafer inside the film through the window of the wafer surface. Thus, grooves for dielectric isolation are formed.
    Next, the front and back negative resist films and the mask oxide film are removed.
    Then, a dielectric isolation oxide film is formed on the surface of the wafer by an oxidation heat treatment.
    Subsequently, polysilicon is grown on the dielectric isolation oxide film, and then the silicon wafer is ground and polished from the back side of the wafer to expose the dielectric isolation silicon island. Thus, a dielectric separated wafer is produced.
    Particularly, in the case where the dielectric separation wafer is the bonded dielectric separated wafer, the active layer wafer having the dielectric silicon island made of silicon produced and the wafer for the support substrate are joined to produce a bonded dielectric separated wafer having the effect of the present invention do. As a result, the present invention can be applied to a bonded dielectric separated wafer in which the deterioration of the quality of the dielectric isolating silicon is not likely to be deteriorated by thermal deterioration by the high temperature CVD method.
    Further, the inventors of the present invention have found that, after polishing the surface of a dielectric separation wafer, polysilicon is deposited (grown) on the surface of the wafer, or SOG (spin-on glass) Is removed by grinding and removing the polysilicon layer or the SOG layer, the present invention has been completed by paying attention to the fact that various problems arising during device manufacturing on the user side are solved.
    A second aspect of the present invention is to provide a dielectric separation wafer capable of planarizing the surface of a dielectric separation wafer and a method of manufacturing the same.
    It is another object of the present invention to provide a method for manufacturing a dielectric separation wafer which does not cause deterioration of quality of silicon islands when the buried polysilicon layer is deposited.
    It is another object of the present invention to provide a method for manufacturing a dielectric separation wafer in which there is little fear that the concave portion of the wafer surface will be remodeled at the time of polishing and removing the polysilicon layer.
    A dielectric separation wafer according to a second aspect of the present invention is a dielectric separation wafer in which a surface of a dielectric separation wafer on which a dielectric isolation silicon island is formed is polished and then a polysilicon layer is formed on the surface of the dielectric separation wafer by CVD, The recessed portion of the wafer surface generated during polishing is buried, and thereafter the polysilicon layer is removed by polishing, leaving the buried portion of the recess.
    The CVD method for forming a polysilicon layer is a method in which a raw material gas containing silicon is introduced into a reaction furnace together with a diluting gas (usually N 2 gas), and the raw material gas is thermally decomposed or reduced on a silicon wafer heated at a high temperature Thereby precipitating the silicon produced. As the compound containing silicon, SiH 2 Cl 2 , SiH 4 and the like are used. Examples of the CVD method include a high-temperature CVD method and a low-temperature CVD method.
    As the reaction furnace, for example, there is a horizontal furnace in which a silicon wafer on a boat fixed in a quartz tube of a transverse length is subjected to resistance heating while gas is introduced. In addition, there is a vertical furnace in which a vertical quartz (SiC) boat containing a silicon wafer is introduced into a bell-shaped quartz (SiC) bell while introducing gas while inducing high-frequency induction heating.
    The thickness of the amorphous silicon layer or polysilicon layer deposited (grown) by the CVD method is preferably 0.2 to 5 탆, more preferably 0.4 to 1.0 탆. When the thickness is less than 0.2 탆, the problem that the step difference does not sufficiently disappear occurs. On the other hand, when the thickness exceeds 5 탆, there arises a problem that the time for planarization polishing becomes unnecessarily long.
    As the polishing solution at the time of polishing the surface of the dielectric separating wafer, for example, an alkaline etching solution such as NaOH or KOH in which 3 to 4 wt% of abrasive grains (SiO 2 ) having an average particle diameter of about 10 to 100 nm is added .
    The polishing amount of the polysilicon layer is an amount enough to abrade and remove the buried portion of the concave portion formed on the surface of the dielectric separation wafer in accordance with the thickness of the polysilicon.
    The dielectric separation wafer may be a bonded wafer obtained by bonding a wafer for an active layer, on which a dielectric-isolated silicon island is formed, and a wafer for the support substrate. Such bonding can employ a well-known wafer bonding technique.
    In the method of manufacturing a dielectric separation wafer according to the second invention, after the surface of the dielectric separation wafer having the dielectric isolation islands formed thereon is polished, a polysilicon layer is formed on the surface of the dielectric separation wafer by CVD, A step of filling a concave portion of the surface of the wafer generated at the time of polishing the surface of the separated wafer; and a step of polishing and removing the polysilicon layer while leaving the buried portion of the concave portion.
    Here, the conditions described for the dielectric separation wafer according to the second invention are also suitable for a method for manufacturing a dielectric separation wafer.
    As a method for forming the amorphous silicon layer or the polysilicon layer, for example, a low pressure CVD method, an atmospheric pressure CVD method, or the like can be employed. The pressure during film formation by the low pressure CVD method is about 10 to 80 Pa.
    In the method of manufacturing a dielectric separation wafer according to the second invention, the polysilicon layer for filling the recess may be formed by a low-temperature CVD method at 550 to 700 占 폚.
    When the temperature is less than 550 ° C, there is a problem that the deposition rate is delayed. On the other hand, when the temperature exceeds 700 캜, the particle diameter of the polysilicon becomes large and it becomes difficult to planarize by later planarization polishing.
    The pressure during film formation by the low-temperature CVD method is 10 to 80 Pa in the low-pressure CVD method and under normal pressure in the atmospheric pressure CVD method.
    Another aspect of the dielectric separation wafer according to the second invention is that the surface of the dielectric separation wafer on which the dielectric isolation islands are formed is polished and then the SOG layer is formed on the surface of the dielectric separation wafer, And then the SOG layer is removed by polishing while leaving the buried portion of the recess.
    As a coating method of SOG (ethyl silicate), for example, spin coating performed while rotating a dielectric separation wafer can be adopted.
    In another aspect of the method for manufacturing a dielectric separation wafer according to the second invention, after the surface of a dielectric separation wafer having a dielectric isolation silicon island formed thereon is polished, SOG is coated on the surface of the dielectric separation wafer and is fired, Forming a SOG layer on the surface of the dielectric wafer by polishing the surface of the dielectric wafer; polishing the SOG layer by abrading the recessed portion of the wafer; to be.
    The coating thickness of the SOG is preferably 0.2 to 2.0 탆, more preferably 0.3 to 0.6 탆. When the thickness is less than 0.2 탆, the filling of the concave portions is insufficient. In the case of a thick film having a thickness of more than 2.0 占 퐉, overcoating is required in the SOG coating method, and there is a problem that thickness unevenness tends to occur.
    The firing of the SOG is performed in an N 2 gas atmosphere such as a furnace, and the alcohol fraction in the SOG is vaporized. The calcination temperature is 200 to 250 DEG C, and when the calcination temperature is less than 200 DEG C, a long time is required for vaporization of the alcohol fraction. Further, even if the temperature exceeds 250 DEG C, there is no particular problem if it is not high temperature (for example, 900 DEG C or higher) at which the dopant diffuses significantly, but this is unnecessary. The baking time of SOG is 30 to 60 minutes.
    According to the second aspect of the present invention, after the surface of the dielectric separation wafer having the dielectric isolation silicon island formed thereon is polished, a polysilicon layer is deposited (grown) on the surface of the dielectric separation wafer by CVD, Followed by baking to form an SOG layer. By doing so, the concave portions generated at the time of surface polishing of the dielectric separation wafer are buried by the polysilicon layer or the SOG layer. Subsequently, the polysilicon layer or the SOG layer is polished away from the surface. At this time, the portion where the concave portion of the wafer surface is buried is left and polished. As a result, the surface of the dielectric separation wafer can be planarized.
    Particularly, as described above, the second invention can be applied to a bonded dielectric separated wafer. Therefore, when compared with the method of producing a dielectric separation wafer in a method in which a non-bonded wafer is not bonded, warpage of the wafer can be suppressed to a small extent and thus the present invention can be applied to a wafer having a large diameter of 5 inches or more.
    When the polysilicon layer for filling recesses is a low-temperature amorphous silicon layer or polysilicon formed by the low-temperature CVD method at 550 to 700 占 폚 in the method of manufacturing a dielectric separation wafer as described above, It is possible to reduce the possibility that the concave portion of the wafer surface is remodeled at the time of polishing removal of the polysilicon layer.
    It is also possible to combine the first invention and the second invention. In this case, both of the first and second aspects of the present invention are effective.
    The present invention relates to a dielectric separation wafer and a manufacturing method thereof.
    Specifically, in the present invention, in the photolithographic process for forming the dielectric isolation grooves, the negative resist applied to the back surface of the silicon wafer is entirely diffused toward the surface side of the wafer peripheral portion, And the vicinity of the periphery of the backside negative resist film is melted and lost even when the developer flows back to the back side of the wafer when developing the surface negative resist film after application of the backside negative resist, The present invention relates to a method of manufacturing a dielectric separation wafer.
    The present invention also relates to a dielectric separation wafer for flattening a recess (step) on a wafer surface formed by separation polishing of a silicon island of a dielectric separation wafer at the time of manufacturing a dielectric separation wafer having a dielectric isolation silicon island, .
    The present application is based on the patent application No.1081084 and the patent application No.1081085, the content of which is incorporated herein by reference.
    BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram of a photolithographic process of a method for manufacturing a dielectric separation wafer according to a first embodiment of the present invention; FIG.
    FIG. 2 is an explanatory view showing a manufacturing process of a bonded dielectric separated wafer according to a third embodiment of the present invention; FIG.
    3 is an enlarged cross-sectional view of a main portion of a bonded dielectric separated wafer produced by a method of manufacturing a dielectric separated wafer according to a third embodiment of the present invention.
    4 is an explanatory view showing a manufacturing process of a bonded dielectric separated wafer according to a fourth embodiment of the present invention;
    5 is an explanatory view showing a manufacturing process of a general bonded dielectric separated wafer;
    6 is an explanatory diagram of a general photolithographic process;
    7 is an explanatory diagram of a conventional pellet lithography process.
    FIG. 8 is an enlarged cross-sectional view of a main part of a bonded dielectric separated wafer produced according to conventional means; FIG.
    BEST MODE FOR CARRYING OUT THE INVENTION [
    Hereinafter, a method of manufacturing a dielectric separation wafer according to an embodiment of the present invention will be described. Here, the junction dielectric separating wafers described above as the prior art will be described as an example. Therefore, the same parts as those shown in Figs. 5 to 8 are denoted by the same reference numerals. Reference numeral 10 denotes a silicon wafer for an active layer wafer, 10A denotes a dielectric isolation island, 11 denotes a mask oxide film, 12 denotes a negative resist film, Reference numeral 13 denotes a dielectric isolation groove, reference numeral 14 denotes a dielectric isolation oxide film, reference numeral 16 denotes polysilicon, 16a denotes a concave portion, 20 denotes a support substrate Reference numeral 30 denotes a low temperature polysilicon layer (polysilicon layer), and reference numeral 300 denotes a SOG layer.
    1 is an explanatory diagram of a photolithographic process of a method of manufacturing a dielectric separation wafer according to the first embodiment of the present invention. The basic steps of the manufacturing method of the dielectric separation wafer of the first embodiment of the present invention are the same as those of the conventional bonded dielectric separation wafer shown in Figs. 5 and 7 described in the prior art. However, the present invention differs from the prior art in part of the basic photolithographic process during the production of the dielectric separation wafer shown in Fig.
    First, a silicon wafer 10 having front and back surfaces mirror-finished, which becomes a wafer for an active layer, is prepared (see Fig. 5 (a)).
    Subsequently, a mask oxide film 11 is formed on the top and bottom surfaces of the silicon wafer 10 (see Fig. 5 (b)).
    Subsequently, a negative resist film 12 in which the window 12a is formed is formed by photolithography.
    Next, the silicon wafer 10 is immersed in an etching solution (IPA / KOH / H 2 O) to anisotropically etch the wafer surface (see FIG. 5C). Thus, a V-shaped dielectric isolation groove 13 is formed on the surface of the wafer.
    Next, the negative resist film 12 is removed, and the exposed mask oxide film 11 is removed (see Fig. 5 (d)).
    Thereafter, a dopant is implanted into the silicon, if necessary, and then a dielectric isolation oxide film 14 is formed on the surface of the wafer by an oxidative heat treatment (see FIG. 5 (e)). As a result, the dielectric isolation oxide film 14 is also formed on the dielectric isolation trench 13.
    Next, the wafer surface is cleaned.
    Subsequently, the seed polysilicon layer 15 is deposited on the surface of the silicon wafer 10 by low-temperature CVD at about 600 캜.
    After cleaning, the high-temperature polysilicon layer 16 is grown thickly on the seed polysilicon layer 15 by the high-temperature CVD method at about 1250 캜 (see Fig. 5 (f)).
    Then, the peripheral portion of the wafer is chamfered, and the back surface of the wafer is planarized as necessary. Subsequently, the high-temperature polysilicon layer 16 on the wafer surface is ground and polished to a thickness of about 30 탆 (see FIG. 5 (g)).
    Thereafter, a low-temperature polysilicon layer 17 having a thickness of about 3.0 탆 is formed on the surface of the wafer by low-temperature CVD at 600 캜. Then, the surface of the low-temperature polysilicon layer 17 Polish.
    On the other hand, a silicon wafer 20 (here covered with a silicon oxide film 21) serving as a wafer for a support substrate is prepared (see FIG. 5 (h)). This is a mirror surface machining of the wafer surface.
    Next, the silicon wafer 10 for the active layer wafer is brought into contact with the mirror faces on the silicon wafer 20 (see FIG. 5 (i)).
    Then, a heat treatment is performed to increase the bonding strength of the bonded wafer.
    5 (j), the outer peripheral portion of the active layer silicon wafer 10 is chamfered, and if necessary, the oxide film 21 of the silicon wafer 20 for the support substrate is subjected to HF cleaning After the removal, the silicon wafer 10 for the active layer is ground and polished. The grinding amount of the silicon wafer 10 is such that the dielectric isolation oxide film 14 is exposed to the outside and the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 on the surface of the high- So that the adjacent silicon islands are completely separated from each other.
    Thus, a bonded dielectric separated wafer is produced.
    The photolithographic process in the first embodiment will be described below. First, the negative resist 12 is spin-coated on the surface of the silicon wafer 10 (see Fig. 1 (a)) on which the mask oxide film 11 is formed, the surface of which is held horizontally.
    Subsequently, in this photolithographic process, the window portion 12a of a predetermined pattern is provided on the negative resist film 12 through the usual prebaking, exposure, development and rinsing (see FIG. 1 (b) ). After that, the silicon wafer 10 may be placed in a baking furnace (not shown), and post baking of the negative resist film 12 on the wafer surface may be performed.
    Thereafter, the silicon wafer 10 on which the window portion 12a is formed is inverted and the negative resist 12A is spin-coated on the wafer backside. At this time, the backside negative resist 12A is completely diffused toward the surface side of the peripheral portion of the wafer to fill the window portion 12a formed in the surface negative resist film 12 existing in the region (see FIG. 1C) .
    Next, the backside negative resist film 12A is exposed to the whole surface, and the backside negative resist film 12A is subjected to crosslinking reaction (see Fig. 1 (c2)). This process is a characteristic feature of the present invention. The cross-linking reaction increases the chemical resistance of the backside negative resist film 12A with respect to the etching solution.
    Thereafter, the entire exposed silicon wafer 10 is immediately turned, and the second developing and rinsing process is performed from the wafer surface side. As a result, the backside negative resist 12A filling the inside of the window portion 12a is cleaned and removed. At this time, the second developing liquid is completely diffused to the back side of the wafer peripheral portion, and a portion of the outer peripheral portion of the backside negative resist film 12 is dissolved (see Fig. 1 (c1)).
    However, as shown in Fig. 1 (c2), the backside negative resist film 12A has already undergone crosslinking reaction by the front exposure, and chemical resistance has been increased. As a result, even if the second developer is deposited near the outer peripheral portion of the backside negative resist film 12A, the resist is not fused.
    Thereafter, the silicon wafer 10 is placed in a baking furnace, and the front and back negative resist 12, 12A are post-baked.
    In the present embodiment, since the active layer wafer 10 having the dielectric isolation silicon island 10A and the junction dielectric wafer for bonding the wafer 20 for the support substrate are employed, the thickness of the polysilicon layer formed by the high- It does not require growth.
    Next, a method for manufacturing a dielectric separation wafer according to a second embodiment of the present invention will be described.
    The manufacturing method of the dielectric separating wafer of the second embodiment is the same as the manufacturing method of the first embodiment except that the application of the surface negative resist 12 to the surface of the silicon wafer 10 of Fig. Then, the silicon wafer 10 is reversed without developing / rinsing the surface negative resist film 12 to face the back side of the wafer. After the backside negative resist 12 is coated on the back surface of the wafer, the film 12 is entirely exposed. Next, the silicon wafer 10 is immediately turned and the surface negative resist film 12 is developed and rinsed to form the window portion 12a, and the front side surface negative resist films 12 and 12A are post-baked.
    In the second embodiment, the developing process of the surface negative resist film 12 can be finished one time without performing the developing process twice as in the first embodiment. As a result, the number of manufacturing steps of the dielectric separation wafer can be reduced.
    Next, a dielectric separation wafer according to a third embodiment of the present invention and a manufacturing method thereof will be described.
    First, a silicon wafer 10 having a mirror-finished surface serving as an active layer wafer is prepared and prepared (Fig. 5 (a)).
    Subsequently, a mask oxide film 11 is formed on the surface of the silicon wafer 10 (FIG. 5 (b)).
    Next, the resist film 12 is deposited on the oxide film 11. Then, a window of a predetermined pattern is formed in the resist film 12.
    A window of the same pattern is formed in the oxide film 11 through the window, and a part of the surface of the silicon wafer 10 is exposed.
    Next, the resist film 12 is removed.
    Further, the silicon wafer 10 is immersed in an etching solution (IPA / KOH / H 2 O) for a predetermined time. As a result, concave portions in a predetermined pattern are formed on the surface of the silicon wafer. Anisotropic etching is performed on the surface of the wafer (Fig. 5 (c)), and a V-shaped dielectric isolation groove 13 is formed.
    Next, the mask oxide film 11 is cleaned and removed with a diluted HF solution (Fig. 5 (d)). At this time, it is also possible to introduce a dopant into the silicon bulk.
    Next, a dielectric isolation oxide film 14 of a predetermined thickness is formed on the surface of the silicon wafer by oxidative heat treatment (Fig. 5 (e)).
    Then, the wafer surface is cleaned.
    Next, the seed polysilicon layer 15 is deposited on the surface of the silicon wafer 10 by the low-temperature CVD method at about 600 캜.
    After the cleaning, the high-temperature polysilicon layer 16 is grown to a predetermined thickness on the seed polysilicon layer 15 by the high-temperature CVD method at about 1250 캜 (Fig. 5 (f)).
    Next, the outer periphery of the wafer is chamfered, and the back surface of the wafer is planarized as necessary.
    Subsequently, the high-temperature polysilicon layer 16 on the wafer surface is ground and polished to a thickness of 30 占 퐉 (FIG. 5 (g)).
    Alternatively, if necessary, the low-temperature polysilicon layer 17 having a thickness of 3 占 퐉 is deposited on the surface of the wafer by low-temperature CVD at 600 占 폚 to polish the surface thereof.
    Meanwhile, a silicon wafer 20 for a support substrate is prepared (FIG. 5 (h)). Next, the silicon wafer 10 for the active layer wafer is superimposed on the silicon wafer 20 so that their mirror faces are superimposed on each other (FIG. 5 (i)).
    Then, the bonded wafer 30 is subjected to a predetermined bonding heat treatment.
    5 (j), the outer peripheral portion of the active layer wafer side is chamfered, and if necessary, the oxide film 21 of the support substrate wafer 20 is removed, and then the surface of the active layer wafer is ground · Polished. The grinding amount of the wafer for the active layer is set until the dielectric isolation silicon island 10A partitioned by the dielectric isolation oxide film 14 is exposed (see also Fig. 8).
    2 (a) and 2 (b) are explanatory diagrams showing a manufacturing process of a bonded dielectric separated wafer according to a third embodiment of the present invention.
    Thus, the bonded dielectric separated wafer shown in FIG. 5 (j) is produced. At this time, on the surface of the active layer wafer, a concave portion 16a having a depth of about 0.3 mu m generated at the time of surface polishing is formed (see also Fig. 8).
    Subsequently, the bonded dielectric wafers were put into a reactor, and SiH 4 , which is a growth gas of a predetermined concentration, was introduced together with a diluting gas (H 2 gas) in the furnace, and an active layer The low-temperature polysilicon layer 30 is laminated on the entire surface of the wafer for a thickness of 0.5 mu m. The pressure during film formation is 50 Pa. As a result, the concave portion 16a is buried by the low-temperature polysilicon layer 30 (see the chain double-dashed line in Fig. 3). Fig. 2 (a) shows such a state.
    Next, Fig. A poly NaOH solution, SiO 2 abrasive grains in only the left, the polishing liquid filled part (30A) of the surface of the silicon layer 30, a concave portion (16a) as shown in 2 (b) And is polished and removed by a well-known polishing apparatus. Specifically, the surface of the dielectric isolation island 10A is polished until the surface thereof is exposed.
    Thus, the surface of the active layer wafer can be planarized. As a result, for example, in the photolithographic process at the time of device fabrication on the user side, the resist on the wafer surface can be uniformly applied. In addition, it is possible to prevent the disconnection of circuit and deterioration of resolution at the time of exposure of the photolithographic process, and to eliminate the possibility that a part of the film is left on the surface of the wafer upon removal of the resist film after exposure. Also in other processes, it is possible to prevent the dust from getting into the concave portion 16a and becoming a dust adsorption site.
    As described above, since the active layer wafer having the dielectric isolation silicon island 10A and the wafer 20 for the support substrate are bonded to each other, a bonded dielectric separated wafer is manufactured. Therefore, the long- High-temperature heating becomes unnecessary. Further, warping of the dielectric separation substrate can be kept small. Since the concave portion 16a is filled with the low-temperature amorphous silicon layer or the polysilicon layer 30 formed by the low-temperature CVD method at 550 to 700 ° C, when the low-temperature amorphous silicon layer or the polysilicon layer 30 is polished and removed It is possible to reduce the possibility that the concave portion 16a is formed on the wafer surface. The low temperature amorphous silicon layer or the polysilicon layer has a smaller crystal grain than the high temperature polysilicon layer.
    Then, in practice, the flatness of the surface of the dielectric separating wafer on the wafer side for the active layer was measured with a needle contact flatness meter.
    The average flatness of the surfaces of the 25 active layer wafers manufactured by the conventional method was 0.24 탆. On the other hand, the average flatness in the case of employing the manufacturing method of the present invention was suppressed to 0.01 μm.
    Next, a dielectric separation wafer according to a fourth embodiment of the present invention and a manufacturing method thereof will be described with reference to Fig. 4 (a) to 4 (c) are explanatory diagrams showing a manufacturing process of a bonded dielectric separated wafer according to a fourth embodiment of the present invention.
    In the fourth embodiment, a method of forming SOG (ethyl silicate) on the surface of the active layer wafer is employed as a method of providing the buried portion 300A for embedding the concave portion 16a on the surface of the active layer wafer Yes.
    That is, as shown in Fig. 4A, the SOG 300 is spin-coated on the surface of the active layer wafer to a thickness of 0.6 mu m. Thereafter, as shown in Fig. 4 (b), the SOG layer 300 is baked and solidified while vaporizing the alcohol in the furnace. Such firing is performed in an N 2 gas atmosphere at a firing temperature of 200 to 250 ° C and a firing time of 30 to 60 minutes. Thereafter, polishing is performed in the same manner as the low-temperature polysilicon layer 30 to planarize the wafer surface (see FIG. 4C).
    In the case of using SOG, the HF-based process can not be performed. This is because when the substrate is immersed in the HF-based solution, the substrate is etched off to its original state at the moment. It is also possible to detect the end of the SOG surface in accordance with the presence or absence of wastage.
    The average flatness of the surfaces of the 25 wafers for the active layer produced by this SOG was measured and found to be 0.02 탆 for 0.24 탆 of the conventional method.
    In the above description, the embodiments are described separately. However, the first and third embodiments, the first and fourth embodiments, the second and third embodiments, the second and the third embodiments, Four embodiments may be combined.
    According to the first aspect of the present invention, since the back side negative resist is applied to the silicon wafer and then the front side negative resist is applied to the silicon wafer, the vicinity of the outer periphery of the negative resist film applied on the back side of the wafer during the development of the surface negative resist after application of the back side negative resist, It is possible to prevent the spoilage.
    In particular, the present invention can be applied to a bonded dielectric separated wafer. In this case, the polysilicon layer formed by the high-temperature CVD method does not require a thick growth.
    According to the second invention, after the surface of the dielectric separation wafer is polished, polysilicon is deposited (grown) on the surface of the wafer by the CVD method, or baked after the SOG is applied, or the recessed portion of the wafer surface is buried . Thereafter, the polysilicon layer or the SOG layer is polished and removed with the buried portion of the recess left, so that the surface of the dielectric separation wafer can be planarized.
    Particularly, when the present invention is applied to a bonded dielectric separating wafer, a bonded dielectric separating wafer is manufactured by bonding a wafer for active layer having a dielectric isolating silicon island and a wafer for supporting substrate, and a concave portion of the surface of the bonded dielectric separating wafer The dielectric separating wafer which does not conform to the bonding method has the following advantages. That is, since the supporting substrate is replaced with a single crystal silicon wafer, the warpage of the wafer can be maintained at 150 탆 or less, for example, even in a large diameter wafer of 5 inches or more.
    When the polysilicon layer for recess filling in the method of manufacturing a dielectric separation wafer is low temperature polysilicon formed by the low temperature CVD method at 550 to 700 캜, when the polysilicon layer is polished and removed, It is possible to reduce the concern that the additional part is re-formed.
    权利要求:
    Claims (8)
    [1" claim-type="Currently amended] The top and bottom surfaces of the silicon wafer were covered with a mask oxide film,
    A resist film having a window formed on the surface of the mask oxide film,
    A window of a predetermined pattern is formed in the mask oxide film using the resist film as a mask to expose a part of the surface of the silicon wafer from this window,
    A portion of the exposed silicon wafer surface is anisotropically etched to form a dielectric isolation groove,
    A dielectric isolation oxide film is formed on the surface of a silicon wafer,
    A polysilicon layer is grown on the dielectric isolation oxide film,
    And a silicon wafer separated from the dielectric isolation oxide film on the polished surface by grinding / polishing the silicon wafer from the back side thereof,
    The step of providing the window-
    Applying a negative resist to the surface of the mask oxide film,
    A step of forming a window of a predetermined pattern in the negative resist film;
    A step of applying a negative resist to the mask oxide film on the back side,
    Subjecting the negative resist film on the back surface side to a front exposure,
    A step of removing the back side negative resist attached to the window of the surface negative resist
    Wherein the dielectric separator comprises a first dielectric layer and a second dielectric layer.
    [2" claim-type="Currently amended] The method according to claim 1,
    Wherein the dielectric separation wafer is a bonded dielectric separated wafer produced by bonding an active layer wafer on which the island of the separated silicon is formed and a wafer for the support substrate.
    [3" claim-type="Currently amended] In the separation wafer of the dielectric,
    The surface of the dielectric separation wafer having the dielectric isolation silicon island formed thereon is polished and then the polysilicon layer is formed on the surface of the dielectric separation wafer by the CVD method to form a concave portion of the wafer surface generated during the surface polishing of the dielectric separation wafer And thereafter the polysilicon layer is polished away by leaving a buried portion of the recess.
    [4" claim-type="Currently amended] The method of claim 3,
    And a bonded wafer obtained by bonding a wafer for an active layer on which a dielectric isolating silicon island is formed on the surface thereof and a wafer for the supporting substrate.
    [5" claim-type="Currently amended] A method of manufacturing a dielectric separation wafer,
    The surface of the dielectric separating wafer having the dielectric isolating silicon island formed thereon is polished and a polysilicon layer is formed on the surface of the dielectric separating wafer by the CVD method to form a concave portion of the wafer surface, A step of embedding,
    And polishing the polysilicon layer by leaving the buried portion of the recess to be removed.
    [6" claim-type="Currently amended] 6. The method of claim 5,
    Wherein the polysilicon layer for recess filling is formed by a low-temperature CVD method at 550 to 700 占 폚.
    [7" claim-type="Currently amended] In the dielectric separation wafer,
    The surface of the dielectric separation wafer having the dielectric isolation silicon island formed thereon is polished and the SOG layer is formed on the surface of the dielectric isolation wafer to fill the recessed portion of the wafer surface that occurred during the surface polishing of the dielectric separation wafer, And the SOG layer was polished by leaving the buried portion of the recess.
    [8" claim-type="Currently amended] A method of manufacturing a dielectric separation wafer,
    The surface of the dielectric separation wafer having the dielectric isolation silicon island formed thereon is polished and then the SOG layer is formed by applying SOG on the surface of the dielectric separation wafer and firing the SOG layer so that the surface of the dielectric separation wafer, A step of embedding a concave portion,
    And a step of abrading and removing the SOG layer while leaving a buried portion of the recess.
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    同族专利:
    公开号 | 公开日
    EP1100124A1|2001-05-16|
    EP1100124A4|2007-05-02|
    WO2000001009A1|2000-01-06|
    US6562692B1|2003-05-13|
    KR100384343B1|2003-05-16|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-06-26|Priority to JP18108498A
    1998-06-26|Priority to JP1998-181085
    1998-06-26|Priority to JP18108598A
    1998-06-26|Priority to JP1998-181084
    1999-06-22|Application filed by 가와이 겐이찌, 미쯔비시 마테리알 실리콘 가부시끼가이샤
    2001-03-26|Publication of KR20010025124A
    2003-05-16|Application granted
    2003-05-16|Publication of KR100384343B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP18108498A|JP3308496B2|1998-06-26|1998-06-26|Manufacturing method of dielectric isolation wafer|
    JP1998-181085|1998-06-26|
    JP18108598A|JP3675642B2|1998-06-26|1998-06-26|Method for manufacturing dielectric separated wafer|
    JP1998-181084|1998-06-26|
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